This invention relates to a high-speed level-shifting circuit for use in propagation of signals between a low-power-level domain and a high-power-level domain, especially in a serial interface of a programmable logic device (PLD), in which the levels may be different from one user application to another.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate serial input/output (I/O) standards, which may be single-ended or differential. Frequently, in such interfaces, a signal propagates between a digital domain and an analog domain. In general, a digital domain has a relatively low-voltage power supply, while an analog domain has a relatively high-voltage power supply. The signal is converted from low-voltage to high-voltage when it travels from the digital domain to the analog domain.
For this purpose, a level-shifting circuit that can be used in high-speed applications is known. However, the known level-shifting circuit has a bottleneck that limits the effective speed or bandwidth at which it can used.
It would be desirable to be able to provide a high-speed level-shifting circuit that is less limited in speed or bandwidth. In addition, many serial protocols are differential, and therefore it would be desirable for the high-speed level-shifting circuit to work with differential signals as well as single-ended signals.